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- W2163370852 abstract "An asynchronous FIR filter, based on a single bit-plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coefficient-set. The proposed architecture has the property that coefficients in a sign-magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs." @default.
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- W2163370852 date "2002-11-13" @default.
- W2163370852 modified "2023-09-23" @default.
- W2163370852 title "A low-power asynchronous VLSI FIR filter" @default.
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- W2163370852 doi "https://doi.org/10.1109/arvlsi.2001.915548" @default.
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