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• W2163835324 abstract "This paper presents a single-chip quad-band GSM/GPRS transceiver with fully-integrated VCOs in a 0.35 /spl mu/m BiCMOS technology. The transceiver consists of an image-rejected low-IF receiver, an OPLL transmitter with TxVCO, a fractional-N frequency synthesizer with a RFVCO and LDO regulators. The receiver has a maximum gain of 100 dB with more than 110 dB dynamic range and the static reference sensitivity is better than -108 dBm. The transmitter delivers 5 dBm output power with 6/spl deg/ peak-to-peak and 2/spl deg/ rms phase errors and the 400 kHz modulation spectrum is better than -65 dBc. The power consumption during receiving and transmitting modes are 68 mA and 120 mA, respectively. This chip is housed in a 56-pin QFN package." @default.
• W2163835324 created "2016-06-24" @default.
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• W2163835324 date "2004-09-28" @default.
• W2163835324 modified "2023-09-27" @default.
• W2163835324 title "A single-chip RF transceiver for quad-band GSM/GPRS applications" @default.
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• W2163835324 doi "https://doi.org/10.1109/rfic.2004.1320643" @default.
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