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- W2164231539 abstract "This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent." @default.
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- W2164231539 date "2007-01-01" @default.
- W2164231539 modified "2023-09-26" @default.
- W2164231539 title "A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers" @default.
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- W2164231539 doi "https://doi.org/10.1109/essderc.2007.4430925" @default.
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