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• W2164315952 abstract "A strategy to analytically model propagation delay in CMOS SCL gates with output buffer is proposed. The model is obtained by a suitable linearization of the circuit and assuming a dominant-pole behavior. The delay expressions obtained are related to design and process parameters in a simple way. Since they also have an evident physical meaning, the model allows deep understanding of the SCL circuit behavior, and hence they are helpful in the earliest design phases. The accuracy of the model has been checked by simulating an SCL inverter under various bias and load conditions. The error obtained in realistic cases is lower than 20%." @default.
• W2164315952 created "2016-06-24" @default.
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• W2164315952 date "2002-11-13" @default.
• W2164315952 modified "2023-09-27" @default.
• W2164315952 title "Delay estimation of SCL gates with output buffer" @default.
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• W2164315952 doi "https://doi.org/10.1109/icecs.2001.957576" @default.
• W2164315952 hasPublicationYear "2002" @default.
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