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- W2164752295 abstract "This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule." @default.
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- W2164752295 date "2006-12-01" @default.
- W2164752295 modified "2023-09-26" @default.
- W2164752295 title "Memory-Efficient Accelerating Schedule for LDPC Decoder" @default.
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- W2164752295 doi "https://doi.org/10.1109/apccas.2006.342426" @default.
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