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• W2165132871 abstract "As FPGAs are increasingly being used for floating- point computing, a parameterized floating-point logarithm oper- ator is presented. In single precision, this operator uses a small fraction of the FPGA's resources, has a smaller latency than its software equivalent on a high-end processor, and provides about ten times the throughput in pipelined version. Previous work had shown that FPGAs could use massive parallelism to balance the poor performance of their basic floating-point operators compared to the equivalent in processors. As this work shows, when evaluating an elementary function, the flexibility of FPGAs provides much better performance than the processor without even resorting to parallelism. The presented operator is freely available from http://www.ens-lyon.fr/LIP/ Arenaire/." @default.
• W2165132871 created "2016-06-24" @default.
• W2165132871 creator A5015632143 @default.
• W2165132871 creator A5035966925 @default.
• W2165132871 date "2006-03-22" @default.
• W2165132871 modified "2023-09-27" @default.
• W2165132871 title "A parameterizable floating-point logarithm operator for FPGAs" @default.
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• W2165132871 doi "https://doi.org/10.1109/acssc.2005.1599948" @default.
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