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- W2165214930 abstract "This paper presents a heuristic approach to the optimal selection of standard cells in VLSI circuit design. We are considering a cell library composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, we select the best templates from the cell library to minimize the total area of the cells under delay constraints. We have found a very successful heuristic approach to attack this discrete optimization problem." @default.
- W2165214930 created "2016-06-24" @default.
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- W2165214930 date "1990-01-01" @default.
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- W2165214930 title "Delay and area optimization in standard-cell design" @default.
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- W2165214930 doi "https://doi.org/10.1145/123186.123301" @default.
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