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- W2165634116 abstract "An new design approach to derive a high throughput systolic array architecture for a prime length type IV discrete cosine transform based on parallel and pipeline processing is presented. This approach is based on a parallel VLSI algorithm that uses a parallel restructuring of type IV DCT. It uses parallel pseudo-circular correlation structures as basic computational forms. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form that have a small number of I/O channels and low I/O bandwidth that can be efficiently implemented into a VLSI chip. A highly efficient VLSI chip can be thus obtained that has good performances in the architectural topology, processing speed, hardware complexity and I/O costs and outperforms others especially in throughput." @default.
- W2165634116 created "2016-06-24" @default.
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- W2165634116 date "2009-07-01" @default.
- W2165634116 modified "2023-09-26" @default.
- W2165634116 title "A parallel VLSI algorithm for a high throughput systolic array VLSI implementation of type IV DCT" @default.
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- W2165634116 doi "https://doi.org/10.1109/isscs.2009.5206090" @default.
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