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- W2165779143 abstract "This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a field-programmable-gate-array (FPGA) based prototype we show a latency of 970 ns between two machines with our virtualized engine for low overhead (VELO). The FPGA device is directly connected to the CPUs by a hypertransport link. The described hardware architecture is optimized for small messages and avoids the overhead typically found with direct-memory access (DMA) controlled transfers. The stateless approach allows to use the hardware unit directly from many threads and processes simultaneously. It provides a secure user level communication with an extremely optimized start-up phase. Micro benchmarks results are reported both based on proprietary API and OpenMPI basis." @default.
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- W2165779143 date "2008-09-01" @default.
- W2165779143 modified "2023-10-16" @default.
- W2165779143 title "VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers" @default.
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- W2165779143 doi "https://doi.org/10.1109/icpp.2008.85" @default.
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