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- W2166597899 abstract "A method for estimating power consumption of digital CMOS VLSI chips is developed. The method estimates the total power consumption of a chip by analyzing separately for different parts of the chip, which are logic circuit, on chip memory, interconnection, clock distribution, and off chip driving. This method makes it possible to estimate the power consumption of a digital CMOS VLSI chip based on gate count, memory size, and logic circuit. An estimation tool, which is implemented in C language, is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions" @default.
- W2166597899 created "2016-06-24" @default.
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- W2166597899 date "2006-03-22" @default.
- W2166597899 modified "2023-09-24" @default.
- W2166597899 title "Power Estimation in Digital CMOS VLSI Chips" @default.
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- W2166597899 doi "https://doi.org/10.1109/imtc.2005.1604125" @default.
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