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- W2167518328 abstract "This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal antilogarithmic converter. A linear approximation algorithm is proposed and simulated in MATLAB models. The maximum absolute error of the proposed decimal antilogarithmic converter is in the range of -0.000999 les Eabsolute les 0.000857 and the maximum percent error is in the range of -0.000715 les Epercent les 0.000691. The proposed decimal-to-decimal antilogarithmic converter is modeled in VHDL and implemented using a Xilinx Virtex-II Pro P30 FPGA device. The converter is implemented using combinational logic only and it computes decimal antilogarithms results in a single clock cycle, running at 53.1 MHz." @default.
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- W2167518328 date "2008-05-01" @default.
- W2167518328 modified "2023-09-22" @default.
- W2167518328 title "A decimal-to-decimal antilogarithmic converter" @default.
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- W2167518328 doi "https://doi.org/10.1109/ccece.2008.4564734" @default.
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