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• W2169184445 abstract "The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A/sub c/) which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A/sub c/ efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm to solve it efficiently. This algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed defect sensitivity map that can assist a physical designer in improving the yield of his/her layout." @default.
• W2169184445 created "2016-06-24" @default.
• W2169184445 creator A5055210733 @default.
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• W2169184445 date "2002-12-30" @default.
• W2169184445 modified "2023-09-23" @default.
• W2169184445 title "An interactive yield estimator as a VLSI CAD tool" @default.
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• W2169184445 doi "https://doi.org/10.1109/dftvs.1993.595763" @default.
• W2169184445 hasPublicationYear "2002" @default.
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