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• W2169353951 abstract "One of the challenging problems in networks-on-chip (NoC) design is optimising the architectural structure of the on-chip network in order to maximise the network performance while minimising the corresponding costs. In this study, a methodology for multi-objective optimisation of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination." @default.
• W2169353951 created "2016-06-24" @default.
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• W2169353951 date "2013-11-01" @default.
• W2169353951 modified "2023-10-01" @default.
• W2169353951 title "Unified multi‐objective mapping and architecture customisation of networks‐on‐chip" @default.
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• W2169353951 doi "https://doi.org/10.1049/iet-cdt.2013.0017" @default.
• W2169353951 hasPublicationYear "2013" @default.
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