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• W2169553754 abstract "In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design." @default.
• W2169553754 created "2016-06-24" @default.
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• W2169553754 date "2009-04-20" @default.
• W2169553754 modified "2023-09-22" @default.
• W2169553754 title "GCS: high-performance gate-level simulation with GP-GPUs" @default.
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• W2169553754 doi "https://doi.org/10.5555/1874620.1874941" @default.
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