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- W2170195508 abstract "The problem of extracting RTL modules from a gate level netlist has many interesting applications in digital design (V.K. Madiseti, 1999; P. Schaumont et al., 1999; K. Singh and P. Subrahmunyam, 1995), because it provides a conceptual description of the circuit. We approach this transformation by solving two subproblems: the identification of potential modules (candidate subcircuits) and testing them for functional equivalence to known high-level modules (subcircuit identification). We present a technique for unique and comprehensive enumeration of subgraphs of an arbitrary graph, as well as a method of recognizing subgraph isomorphisms. Combined, these results provide a solution to the problem of candidate subcircuit enumeration. These techniques provide both theoretical and practical contributions within design automation and graph theory." @default.
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- W2170195508 date "2002-11-13" @default.
- W2170195508 modified "2023-09-26" @default.
- W2170195508 title "Efficient algorithms for subcircuit enumeration and classification for the module identification problem" @default.
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- W2170195508 doi "https://doi.org/10.1109/iccd.2001.955082" @default.
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