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- W2170216372 abstract "We present a method for verifying the realizability of a timing diagram, ensuring the synthesis of the underlying interface is possible. If necessary, a heuristic is introduced to render explicit hidden timing constraints implied by the specification. A relative schedule of output events is computed, accepting input events from the complete timing space defined by the assumed constraints on the environment." @default.
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- W2170216372 date "2002-11-27" @default.
- W2170216372 modified "2023-09-25" @default.
- W2170216372 title "Synthesis of interface controllers from timing diagram specifications" @default.
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- W2170216372 doi "https://doi.org/10.1109/cicc.1998.694913" @default.
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