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- W2170226427 abstract "This paper proposes a single-phase partially-adiabatic logic family and compares its energy characteristics with other adiabatic families by simulating a full-adder (FA) and an 8-bit carry-lookahead adder (CLA). Full-adder simulation results show that the proposed family uses up to 79% less energy compared to its CMOS equivalent and up to 67% less than other adiabatic implementations. The proposed 8-bit adiabatic CLA performs at least as well as the next best implementation while using a single phase clock instead of a four-phase clock." @default.
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- W2170226427 date "2013-08-01" @default.
- W2170226427 modified "2023-09-25" @default.
- W2170226427 title "Arithmetic circuits using new single-phase partially-adiabatic logic family" @default.
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- W2170226427 doi "https://doi.org/10.1109/mwscas.2013.6674573" @default.
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