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- W2170525675 abstract "In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the parallel compressor the performance of the circuit is increases." @default.
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- W2170525675 date "2012-06-30" @default.
- W2170525675 modified "2023-10-18" @default.
- W2170525675 title "Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic" @default.
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- W2170525675 doi "https://doi.org/10.5120/7169-9750" @default.
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