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- W2171482844 abstract "Early power estimation requires one to estimate the area (gate count) of a design from a high-level description. We propose a method to do this that makes use of the concept of Boolean networks (BN) and introduces an invariant area complexity measure which captures the gate-count requirement of a design. The method can be adapted to be used at different points on the area/delay tradeoff curve, with different synthesizer/mapper tools, and different target gate libraries. The area model is experimentally verified and tested using a number of ISCAS and MCNC benchmark circuits and two different target cell libraries, on two different synthesis systems." @default.
- W2171482844 created "2016-06-24" @default.
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- W2171482844 date "2002-01-01" @default.
- W2171482844 modified "2023-09-26" @default.
- W2171482844 title "High-level area estimation" @default.
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- W2171482844 doi "https://doi.org/10.1145/566408.566479" @default.
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