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• W2171856294 abstract "This paper demonstrates a method to allow rapid design from a high level VHDL program down to a simple netlist. Each stage of the design process generates a complete design representation as the behavioral axis of the Y-chart is descended. These design representations can be simulated to verify operation at each stage. The result is a fast and efficient method for digital design. >" @default.
• W2171856294 created "2016-06-24" @default.
• W2171856294 creator A5042204382 @default.
• W2171856294 creator A5072785679 @default.
• W2171856294 date "2002-11-19" @default.
• W2171856294 modified "2023-09-22" @default.
• W2171856294 title "A practical method for high-level synthesis of combinational logic from VHDL" @default.
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• W2171856294 doi "https://doi.org/10.1109/ssst.1995.390555" @default.
• W2171856294 hasPublicationYear "2002" @default.
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