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- W2178748579 abstract "Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with variable carry-skip. An analysis shows that the carry-skip delay in a Manchester adder block is linearly proportional to the block size. The approach provides a general paradigm for analysis and design, applicable to different models of ripple-propagation and carry skip.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W2178748579 date "1990-01-01" @default.
- W2178748579 modified "2023-09-26" @default.
- W2178748579 title "Analysis and design of CMOS Manchester adders with variable carry-skip" @default.
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- W2178748579 doi "https://doi.org/10.1109/12.57038" @default.
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