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- W2182163205 abstract "Finite field multipliers over GF(2 m ) are widely used in applications like elliptic curve cryptography (ECC) and error control coding systems. These real time applications require an efficient hardware design for polynomial-based multiplication. In this paper, an efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP) is designed. The paper presents a cut-set retiming technique to reduce the critical-path to one XOR gate delay. This technique is highly useful for pipelining digital circuits to reduce the critical path. This paper also presents a novel register- sharing technique and merging of systolic structures to reduce the register requirements and the latency in the systolic structure." @default.
- W2182163205 created "2016-06-24" @default.
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- W2182163205 date "2013-01-01" @default.
- W2182163205 modified "2023-09-27" @default.
- W2182163205 title "An Efficient Systolic Multiplier for GF (2 m ) Based On" @default.
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