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- W2182562678 abstract "The timing model in VHDL was developed to allow very sophisticated modelling of complex inter-process interactions that occur at the system level. The unique characteristics of this model allow timing computations to be freely mixed between behavioral and structural elements of the design. However, this flexible model creates problems for typical ASIC designers since there is no industry accepted standard practise for the representation of timing data in VHDL models or libraries. Furthermore, language restrictions make delay calculations that are dependent on connectivity data cumbersome and inefficient while concepts that are familiar to ASIC designers, such as pin-to-pin timing, are difficult to express in VHDL and generally alien to the underlying timing model of the language." @default.
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- W2182562678 date "1992-01-01" @default.
- W2182562678 modified "2023-09-27" @default.
- W2182562678 title "Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design" @default.
- W2182562678 doi "https://doi.org/10.1007/978-1-4615-3562-1_7" @default.
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