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- W2183373953 abstract "Read stability and read speed in SRAM cell are most likely problems in SRAM. Access transistors used to access the basic latch consumes unwanted time to read the cell during read operation, moreover external noise may corrupt the cell data. To overcome this problem the 10T SRAM cell design has been introduced in this research work. The paper here focuses on the analysis of read behaviour of the cell structure using cadence tool at 45nm technology, and compared with the reported basic 6T structure. While the conventional 6T SRAM cell is equipped with word line for both read and write access, the 10T SRAM cell here uses a different read enable line to read the stored bit. This allows the memory element to remain isolated from the external disturbance, in addition to this, the additional time required to activate the access transistors is not required as the read operation in this cell does not require it." @default.
- W2183373953 created "2016-06-24" @default.
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- W2183373953 date "2014-01-01" @default.
- W2183373953 modified "2023-09-26" @default.
- W2183373953 title "Modelling and Simulation of Low Power SRAM Cell with Improved Read Speed at 45nm Technology" @default.
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