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- W2183670124 abstract "Two of the key challenges according to the 2001 International Technology Roadmap for semiconductors for the source/drain extension junction at the 65-70 nm node and beyond are production of junctions between 10 and 19 nm with sheet resistance values between 760 to 830 Ω/□ for low parasitic source/drain series resistance [1]. Ultra-shallow 49 BF 2 + and 11 B + implants (4.5 keV and 500 eV respectively, 1.0.10 15 cm -2 ) were implanted at room temperature into 73 Ge + (30 keV, 1.0.10 15 cm -2 ) pre-amorphized Si. In contrast to fast spike anneals [2, 3] a simple alternative approach for the formation of ultra-shallow junctions with boron was chosen, consisting of a low-temperature (600-800°C, 5-90 s) solid-phase epitaxial growth process in a standard rapid thermal annealing system with tightly controlled gaseous ambient (NH 3 , Ar, O 2 ). The advantage of this technique is that boron changes over to the electrically-active substitutional site during the regrowth process while dopant diffusion within the lattice is suppressed/minimized by the low temperature process." @default.
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- W2183670124 date "2003-01-01" @default.
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- W2183670124 title "Rapid thermal solid phase epitaxy annealing for ultra-shallow junction formation" @default.
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