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• W2185086915 abstract "The increasing prominence of portable systems and the need to limit power consumption in very high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor ,digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. In this paper, branch based -pass transistor logic or ULPFA full adder and High performance Low power full adder is designed and compared with the existing logics such as CPL and DPL .The adders which is designed is implemented in 8x8 vedic multiplier and the parameters like area ,transistor count and power dissipation are compared by using Tanner EDA tool." @default.
• W2185086915 created "2016-06-24" @default.
• W2185086915 creator A5037829315 @default.
• W2185086915 date "2013-01-01" @default.
• W2185086915 modified "2023-09-27" @default.
• W2185086915 title "Design Of Efficient Vedic Multiplier by the analysis of" @default.
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