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- W2185301866 abstract "Themain challenge ofSmart PowerIntegrated Circuits lies inoperating simultaneously on a same chip apowerdevice anditscontrol circuitry Tothis purpose, static anddynamic isolation between these twoactiveparts arerequired A self isolated CMOS/DMOStechnology where thedramofthevertical DMOS iscoincident withthesubstrate (N-epilayer) oftheCMOS circuitry provides a costeffective staticisolation However, voltage transients induced dunng thepowerdevice switching canbecapacitively coupled totheCMOScircuitry andlatch-up can beinitiated Instead ofintroducing supplementary technological steps, adesign based solution isproposed toimprove dynamic isolation andthenlatch-up immunity [1] Such ashielding is obtained byletting float thevoltage ofthePwell oftheCMOStechnology 1.SMART POWER COMPATIBLEFLOATINGWELL CONCEPT InaCMOStechnology, themostdangerous parasitic bipolar transistor asfar aslatch-up initiation istheparasitic vertical bipolar (PVB) associated withthewellofthetechnology In manycasesandparticularly m VLSIcircuits, usinggrounded body tiesinthewell isthebest solution toavoid latch upinitiation However, inthecaseofpowerintegrated circuits, the parasitic transient can besuchthat even withgrounded body ties, thewelldoesnotremain equipotential andactivation ofthePVBoccursThegrounded body tietherefore supplies the PVBwith asmuchbase current asrequired andlatch-up can beinitiated andbefatal forthe circuit" @default.
- W2185301866 created "2016-06-24" @default.
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- W2185301866 date "1992-01-01" @default.
- W2185301866 modified "2023-09-24" @default.
- W2185301866 title "Floating WellBasedDesign Methodology AimedtoImprove Latch- upImmunity ina SmartPowerTechnology" @default.
- W2185301866 hasPublicationYear "1992" @default.
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