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• W2185328104 abstract "Dielectric breakdown and oxide and interface charge trapping set the scaling limits for thin oxides. Oxide leakage is far from being the limit. Dielectric breakdown is modeled by hole trapping at weak sites with local, above-average current density or large hole trap density. This model predicts a linear relationship between In tgD and 1/F rather than E. It provides a framework for predicting oxide reliability as a function of area and stress condition from limited data. Csing this model and the field experience of thinoxide EEPRO.Zl. it is estimated that 0.01% failure per thousand hour is ach1eLable with 9.5 nm oxides at 5V. This is adequate for 1M-bit DR.44<. Charge trapping and interface trap generation sets a slightly less restrictive limit for gate oxides. Defect reduction holds promise for improving oxide reliability. New dielectrics will probably be necessary at 4%-bit level unless 10 @m2 capacitors are available or cell operation is changed. 6.5 nm oxide should be acceptable for 3.3V operation. Again EEPROlls will provide the real-life test for production thin oxide at that thickness." @default.
• W2185328104 created "2016-06-24" @default.
• W2185328104 creator A5048128782 @default.
• W2185328104 date "1985-01-01" @default.
• W2185328104 modified "2023-09-27" @default.
• W2185328104 title "THIN OXIDE RELIABILITY (Invited Paper)" @default.
• W2185328104 hasPublicationYear "1985" @default.
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