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- W2185646925 abstract "Based on an incremental path search algorithm, this paper addresses the problem of longest combinational paths selection for performance optimization at physical level. A realistic evaluation of gate delay and controlled sizing techniques are used to manage the circuit path sizing alternatives, such as delay or powedarea constraints. The efficiency of this technique is demonstrated and also illustrated on several ISCAS'85 benchmark circuits. A comparison is given between regular sizing altematives to local optimization steps controlled by specific indicators." @default.
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- W2185646925 date "1998-01-01" @default.
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- W2185646925 title "PAT SIZING BASED ON INCREMENTAL TECHNI" @default.
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