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- W2185934810 abstract "A new algorithm forthemultiplication oftwo elements inGF(2m)basedonthemodified Booth's algorithm is presented. Theproposed algorithm permits efficient realization ofthemultiplexer-based bit-parallel multiplication using iterative arrays. Thelatency ofthemultiplier has3m/2clock cycles. For theestimated complexity oftheproposed multiplier, wetakeinto thetransistor countusing astandard CMOS VLSIrealization. Ouranalysis showsthat, intermsofthetimeandthespace complexities, themultiplexer-based arrayarchitecture isthe better choice forourproposed bit-parallel systolic multiplier. KeywordsBooth's algorithm, bit-parallel systolic multiplier" @default.
- W2185934810 created "2016-06-24" @default.
- W2185934810 creator A5058455877 @default.
- W2185934810 creator A5088009977 @default.
- W2185934810 date "2006-01-01" @default.
- W2185934810 modified "2023-09-27" @default.
- W2185934810 title "NewBit-Parallel Systolic Multiplier overGF(2m) UsingTheModified Booth's Algorithm" @default.
- W2185934810 cites W2102291315 @default.
- W2185934810 hasPublicationYear "2006" @default.
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