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- W2186023645 abstract "This paper presents a new methodology for the syn- thesis of high performance flexible datapaths, targeting compu- tationally intensive digital signal processing kernels of embedded applications.Theproposedmethodologyisbasedonanovelcoarse- grained reconfigurable/flexible architectural template, which en- ables the combined exploitation of the horizontal and vertical par- allelism along with the operation chaining opportunities found in the application's behavioral description. Efficient synthesis tech- niques exploiting these architectural optimization concepts from a higher level of abstraction are presented and analyzed. Exten- sive experimentation showed average latency and area reductions up to 33.9% and 53.9%, respectively, and higher hardware area utilization, compared to previously published high performance coarse-grained reconfigurable datapaths." @default.
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- W2186023645 date "2011-01-01" @default.
- W2186023645 modified "2023-09-27" @default.
- W2186023645 title "High Performance and Area Efficient Flexible" @default.
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