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- W2186251134 abstract "This paper presents a new digital pulsewidth mod- ulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM archi- tecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this archi- tecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique re- lies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board." @default.
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- W2186251134 date "2009-01-01" @default.
- W2186251134 modified "2023-10-13" @default.
- W2186251134 title "Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth" @default.
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