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- W2186669362 abstract "Capacitive coupling istheprimary source ofnoise innanometer technology digital CMOS VLSIcircuits. It becomesworsewithtechnology scaling. Theinterconnect capacitive crosstalk noisecanbe characterized by two parameters: peaknoisevoltage, anddelayuncertainty. Delayuncertainty optimization canbeseenasasubset of interconnect delayoptimization. Thispaperaddresses the problemofordering andsizing parallel wiresina single metallayer within aninterconnect channel ofagiven width, suchthatcross-capacitances areoptimally sharedfor simultaneous noise anddelay minimization. Using anElmore delaymodelincluding crosscapacitances fora bundleof wiresandwell-known crosstalk models, we showthat symmetric hill wireordering according tothestrength of signal drivers, whichisknowntooptimize channel timing characteristics, canbeusedalsoforminimizing channel noise metrics. Examples using state-of-the-art circuits in65- nanometer technology areanalyzed anddiscussed." @default.
- W2186669362 created "2016-06-24" @default.
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- W2186669362 date "2006-01-01" @default.
- W2186669362 modified "2023-09-27" @default.
- W2186669362 title "Aneffective technique forsimultaneous interconnect channel delayand noisereduction innanometer VLSIdesign" @default.
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