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- W2187079079 abstract "With bandwidth needs growing from one system generation to the next, the external memory interface must keep up with performance requirements while staying within the maximum power dissipation constraints inevitable in many applications. For higher-bandwidth systems, package size and pin count become limiting factors so I/Os must be used efficiently. All I/Os in the UltraScale architecture are memory interface capable, and the architecture allows I/O bank sharing of two interfaces. This provides the flexibility needed to simplify system design and maximize aggregate memory bandwidth per FPGA. This white paper describes the types of innovative implementations available to designers using the UltraScale FPGA families. The UltraScale architecture enables building high-performance, lower-power 2400 Mb/s DDR4 interfaces that are flexible enough to meet high-bandwidth, FPGA-based system requirements." @default.
- W2187079079 created "2016-06-24" @default.
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- W2187079079 date "2014-01-01" @default.
- W2187079079 modified "2023-09-27" @default.
- W2187079079 title "High-Performance, Lower-Power Memory Interfaces with UltraScale Architecture FPGAs" @default.
- W2187079079 hasPublicationYear "2014" @default.
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