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- W2187484851 abstract "FURTHER PERFORMANCE IMPROVEMENTS in power GaAs FETs at Ku-band and higher frequencies must be accompanied by improved circuit techniques. Conventional cell combining and matching techniques are simply inadequate when applied to the problem of multiple cell combining at Ku-band frequencies. Due to the low impedance level, cell phasing and interaction problems, the number of cells which can be combined successfully decreases rapidly with increasing frequency. An approach is required that applies circuit-level power combining concepts (integral isolation) to the problem of cell combining to yield high combining efficiency. This paper will describe a chip-level cell combining technique, with integral isolation characteristics, which attempts to solve these problems. The approach is illustrated in Figure 1. The cell combiner is implemented directly on the chip carrier, resulting in a compact (active area of approximately 100 x 160mils for the 6-cell combiner at 15GHz) power FET carrier. The circuit consists of the FET cell array sandwiched between an input power divider and an output power combiner. The divider/combiner circuit consists of a 2-section casczde of a 2-way and a 6-way circuit. Each section is nominally 90 m electrical length at the design center frequency. The 2-way circuit, which is part of the external matching network, is a conventional binary Wilkinson divider. The second section, which consists of an array of six low impedance transmission lines and five isolation resistors, forms a planar version of the radial line combiner’. The 6-way divider circuit is fabricated on a thin sapphire substrate adjacent to the FET chip to minimize parasitic inductances. The thin sapphire substrates (4 and lOmils thick for the input and output respectively) are required to realize the low impedance transmission lines in a transverse dimension equal to the cell array width of 2.3mm. This approach results in a uniform phase front with minimum phase error across the cell array. The equivalent circuit of the input divider is shown in Figure 2. The approach is similar in concept to the circuit-level combiner recently proposed . The characteristic impedances of the 2-section divider network are selected to form a 2-section impedance transformer for the even mode to transform the series resonant gate circuit to 50a. The isolation resistors are selected to terminate maximally the 5 independent odd modes that a 2" @default.
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- W2187484851 date "1980-01-01" @default.
- W2187484851 modified "2023-09-26" @default.
- W2187484851 title "SESSION VII: MICROWAVE AMPLIFIERS" @default.
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