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- W2187909389 abstract "After DLL islock, thetotal delay ofwholedelay line isthesame as input clock period. Thispaper presents anall-digital Delay-Locked Loop(DLL)for DDR SDRAM controller applications. Thepresented all-digital, cell- However, iftherequired numbers ofoutput multi-phase signals based, DLL-based five-phase multi-phase clockgenerator can areincreased ortherequired maximumoperating frequency si generate therequired fixed timing delay (tSD)forDDR SDRAM increased, DLL architectures [3,5]willfacedifficult design controller tocapture theoutput data(DQ)correctly. Theproposedchallenges tobuilda highresolution delaycellwithminimum DLL-based multi-phase clock generator architecture canlocktothe intrinsic delayrequirement. As a result, theoperating rangeof harmonic ofinput clock period andstill getacorrect multi-phase previous DLLisseverely limited. clock output. Hencethedesign challenges tobuild ahighresolution delay line withminimumintrinsic delay canbereduced. SimulationInthis paper, thenewDLL-based multi-phase clock generator results andchipmeasurement results showthat theproposed DLL architecture isproposed tolettheDLLlocktoharmonic oftheinput cangenerate desired tSDdelay witherror < 7.6%). Thepower clock period andcanstill getacorrect multi-phase clock output. The consumption oftheproposed DLL is4.1mW(atDDR-200) andis proposed architecture canreduce thedesign challenges tobuild a 9.0mW(at DDR-400). highresolution delay line withminimumintrinsic delay. Hencethe frequency operating range ofDLL canbeimproved." @default.
- W2187909389 created "2016-06-24" @default.
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- W2187909389 date "2006-01-01" @default.
- W2187909389 modified "2023-09-24" @default.
- W2187909389 title "AnAll-Digital Delay-Locked LoopforDDR SDRAM Controller Applications" @default.
- W2187909389 hasPublicationYear "2006" @default.
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