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- W2188208716 abstract "With the advancement of technology, a processor is required to have high speed. Multiplication is a critical operation of Digital Signal processing(DSP) applications(like DFT, FFT, convolution etc), Arithmetic and logic unit(ALU), and Multiply and Accumulate(MAC) unit(which is basically a multiplier itself). Speed Multiplication is thus an essential requirement to increase the performance of processor. In this paper, we are presenting a multiplier, in which the basic multiplication is performed using one of the techniques of Mathematics, and the accumulation of partial products is done using a specific design. Both the design and the vedic technique, results in a high speed multiplier. Mathematics is based on 16 sutras, out of which we are using Urdhva triyagbhyam sutra. In this technique intermediate products are generated in parallel, that makes multiplication faster. We have synthesized our design using Xilinx ISE tool and compared its speed with Modified Booth Wallace Multiplier, High speed Multiplier by Ramesh Pushpangadam and Vedic Mathematics based Multiply Accumulate Unit by Kabiraj Sethi. Our proposed Design seems to have better speed." @default.
- W2188208716 created "2016-06-24" @default.
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- W2188208716 date "2014-01-01" @default.
- W2188208716 modified "2023-09-27" @default.
- W2188208716 title "Design of High Speed Multiplier using Vedic Mathematics" @default.
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