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- W2188331567 abstract "For wafer testing, high parallelism is important in order to reduce test costs. However, increasing parallelism is becoming more difficult because there are limitations to how much the parallelism can be increased with design changes. To solve the limitations, wafer level test schemes based on the network-on-chip (NOC) have been developed. However, connecting to one device under test (DUT) has a reliability problem in which fault distribution causes good-DUT to be improperly tested is becoming a concern. In this paper, a new MPT method is proposed which achieves both its high parallelism and reliability with BT algorithm. The experiment results show that the proposed method achieves the nearly 100% reliability without affecting yield." @default.
- W2188331567 created "2016-06-24" @default.
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- W2188331567 date "2013-01-01" @default.
- W2188331567 modified "2023-09-25" @default.
- W2188331567 title "A Reliable Massively Parallel Testing Method for Wafer Testing" @default.
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