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- W2188486588 abstract "This paper presents an integrated, compiler-driven approach to digital chip design that automates scan-based design and test pattern generation for 100% stuck-at fault coverage. The approach combines language-based design capture, logic synthesis and test pattern generation; and it is especially well suited for designs where reducing design time is more important than minimizing silicon area. The necessary research and development associated with the systenl was highly leveraged by joint cooperative efforts of a multidisciplined team, combining both industrial and institutional perspectives." @default.
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- W2188486588 date "1989-01-01" @default.
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- W2188486588 title "Synergy of Synthesis and Test" @default.
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