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- W2188572505 abstract "`The single-bit full adder is one of the main componentsin almost all logic structures. The performanceof logic structures is highlydependenton the adder cells. This paper discusses the performance of single-bit full adders and presents a performance analysis for those cells in CMOS technology. Fourteen single-bit full adders and three new adders, a total of different adder cells, are analyzed in terms of power and delay using , and m TSMC CMOS technology. In addition, this paper discusses the charging-capabilityparameter of the adder cells, which represents the fan-outof each cell. The charging-capability parameter is capable of describing the performanceof the adder cell in a large, as yet unbuilt structure. Hence, the performance analysis of the single-bit full adderrelates the design to power, delay, and charging capability of the logic components." @default.
- W2188572505 created "2016-06-24" @default.
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- W2188572505 date "2003-01-01" @default.
- W2188572505 modified "2023-09-26" @default.
- W2188572505 title "Low-power single-bit full adder cells Cellules d'addition compl ` ete 1-bit ` a faible puissance" @default.
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