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- W2189530454 abstract "equidistance clocks forsamplers andtheDP-PLL's phaseis rotated digitally bycodes generated fromadigital filter. Since A dualphasefrequency detector phase-locked loop(PLL) theclockfrequency fromthemainPLL is1.25GHz, the architecture formulti-lane 5Gbpsserial linkreceiver is bandwidth oftheDP-PLLcanbesettobeveryhighmaking demonstrated using 0.1L3um CMOS.ThePLL's8multiphase theloopfilter areasmall thusreducing thetotal area. Thistop clocks canberotated altogether digitally withrespect toa architecture camefromtheadjPLL. single fixed phaseclock fromamainPLL.Thephase step Theblock diagram oftheDP-PLLisalsoshowninFig. 1. resolution is1115ofaunitbitinterval andtherotation is TherearetwoPFD'sandtwoweighted charge pumps.The achieved byadding onlyoneadditional phase-frequency input clocks forbothPFD'sareselected bydigital filter block detector (PFD) andacharge pump.Thermsjitter is1.2psusing 2-to-I muxes.Coarsephase selection isdonebythis for5Gbpsserial linkoperation. Thenew PLL occupiesmuxselection. UpperPFDinputs are(p0 andq4andthelower 0.015mm2 andconsumes 3mAfroma1.2Vsupply. ThesmallPFDinputs are(p2 and(p6. Theselected clocks arecompared areaandlowpowernature ofthearchitecture issuitable for withthe1.25GHz clock fromthemainPLL.Thetwocharge receivers inmulti-lane serial links." @default.
- W2189530454 created "2016-06-24" @default.
- W2189530454 creator A5015548248 @default.
- W2189530454 creator A5084242035 @default.
- W2189530454 date "2007-01-01" @default.
- W2189530454 modified "2023-09-22" @default.
- W2189530454 title "ADualPFDPhase Rotating Multi-Phase PLLfor5GbpsPCIExpress Gen2Multi-Lane Serial LinkReceiver inO.13umCMOS" @default.
- W2189530454 hasPublicationYear "2007" @default.
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