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- W219305020 abstract "Dynamic power-gating has been shown to reduce FPGA static leakage power significantly. In this paper, we propose a high-level synthesis (HLS) compiler-assisted framework that automatically detects the hierarchical power-gating opportunities, and turns off accelerators when they are not required. Unlike previous work which considers turning off entire accelerators when they are not required, our technique is more fine-grained, in that it allows turning off a portion of an accelerator when other parts of an accelerator are running. Results on CHStone benchmarks show that hierarchical power-gating can save up to 31 % of static energy when the parent and descendant accelerators are power-gated independently. An additional savings of up to 25 % can be achieved if the parent accelerator is power-gated while the sub-accelerator runs." @default.
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- W219305020 date "2015-01-01" @default.
- W219305020 modified "2023-10-18" @default.
- W219305020 title "Hierarchical Dynamic Power-Gating in FPGAs" @default.
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- W219305020 doi "https://doi.org/10.1007/978-3-319-16214-0_3" @default.
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