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• W2198157070 abstract "This paper investigates the optimization of sleep mode energy consumption for ultra-low V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> CMOS circuits, which is motivated by our findings that minimization of sleep mode energy holds great potential for reducing total energy consumption. We propose a unique approach of using a power gating switch (PGS) in ultra-low V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> regimes. Unlike the conventional manner of using PGSs, our optimization suggests using minimal-sized PGSs with a slightly higher V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> to compensate for voltage drop across the PGS. In SPICE simulations, this reduces total energy consumption by ~125× compared to conventional approaches. The effectiveness of the proposed optimization is also confirmed by measurements taken from an ultra-low power microprocessor. Additionally, the feasibility of using minimal PGSs in ultra-low V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>dd</sub> regimes is investigated using SPICE simulations and silicon measurements." @default.
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• W2198157070 date "2012-04-01" @default.
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• W2198157070 title "Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{rm dd}$ Operation" @default.
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• W2198157070 doi "https://doi.org/10.1109/tvlsi.2011.2109069" @default.
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