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- W2199481013 abstract "This paper proposes a novel Gm−C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is −114.1 dBc/Hz with lower Gm−C bandwidth and −111.7 dBm/C with higher Gm−C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm−C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage." @default.
- W2199481013 created "2016-06-24" @default.
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- W2199481013 date "2012-08-01" @default.
- W2199481013 modified "2023-09-25" @default.
- W2199481013 title "Chip design of a 5.8-GHz fractional- <i>N</i> frequency synthesizer with a tunable <i>G</i> <sub> <i>m</i> </sub> − <i>C</i> loop filter" @default.
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- W2199481013 doi "https://doi.org/10.1088/1674-1056/21/8/084210" @default.
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