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- W2201736731 abstract "This paper presents the design and evaluation of a large scale template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerator that processes correlation algorithm for Timing Synchronization (TS) required in Orthogonal Frequency-Division Multiplexing (OFDM) receivers. The CGRA works as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor. The CGRA accelerator is composed of 80 reconfigurable Processing Elements (PEs) to compute 80-point correlation in 1.8 μs when synthesized on an Field Programmable Gate Array (FPGA). The power consumption is estimated by simulating the postfit gate-level FPGA netlist of the TS accelerator followed by evaluation and comparison with other state-of-the-art platforms in terms of multiple performance metrics." @default.
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- W2201736731 date "2015-10-01" @default.
- W2201736731 modified "2023-09-26" @default.
- W2201736731 title "Design and evaluation of correlation accelerator in IEEE-802.11a/g receiver using a template-based Coarse-Grained Reconfigurable Array" @default.
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- W2201736731 doi "https://doi.org/10.1109/norchip.2015.7364374" @default.
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