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- W2214778331 abstract "A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption." @default.
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- W2214778331 date "2013-01-01" @default.
- W2214778331 modified "2023-09-26" @default.
- W2214778331 title "A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature" @default.
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- W2214778331 doi "https://doi.org/10.1007/978-3-642-41635-4_26" @default.
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