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• W2221186049 abstract "Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$^{2}$</tex> </formula> , program time is 700 us and I/O rate is 1 Gb/s." @default.
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• W2221186049 date "2016-01-01" @default.
• W2221186049 modified "2023-10-18" @default.
• W2221186049 title "A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate" @default.
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• W2221186049 doi "https://doi.org/10.1109/jssc.2015.2474117" @default.
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