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• W2222292553 abstract "This paper reviews the state-of-the-art of high switching frequency, integrated DC–DC converters and presents the main trade-offs and challenges emerging from this review. Various converter structures (1-phase buck, 2-phase buck, 2-phase coupled buck and 3-level converter) are then discussed and analyzed through simulation from a losses point-of-view. Considering the review, the architecture analysis and the technology model, 4 converters are designed for a given set of specifications: 3.3–1.2 V, 280 mA output current at high switching frequency (100–200 MHz) in 40 nm bulk CMOS. A cascode power stage is used in order to enhance power conversion efficiency, and 1-phase and 2-phase structures are designed. Post-layout simulation results are presented, showing an efficiency above 90 % for a 2-phase converter." @default.
• W2222292553 created "2016-06-24" @default.
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• W2222292553 date "2016-01-06" @default.
• W2222292553 modified "2023-10-18" @default.
• W2222292553 title "A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS" @default.
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• W2222292553 doi "https://doi.org/10.1007/s10470-015-0683-z" @default.
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