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- W2222385999 abstract "This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 m CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances." @default.
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- W2222385999 date "2012-01-01" @default.
- W2222385999 modified "2023-09-26" @default.
- W2222385999 title "Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications" @default.
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- W2222385999 doi "https://doi.org/10.1088/1674-4926/33/1/015006" @default.
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