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• W2222414310 abstract "As digital systems grow in complexity, designers are facing unprecedented challenges, such as managing power, handling of variability, and ensuring robustness in the presence of soft errors and noise. If not addressed, these challenges are expected to become major bottlenecks in less than a decade. This thesis presents a unified approach for addressing fault-tolerance, timing-robustness, and low dynamic power in global communication. Asynchronous communication is targeted, because of its inherent flexibility and modularity. Three new families of delay-insensitive codes are introduced. Each of the codes assumes the simple and widely-used return-to-zero (RZ) communication protocol. First, new error- correcting unordered (ECU) codes are proposed, based on an existing Zero-Sum code. This code combines the timing-robustness of delay-insensitive (i.e., unordered) codes with the fault-tolerance of error-correcting codes (providing 1-bit error correction or 2-bit detection). In comparison to the best existing systematic ECU code by Blaum and Bruck, a basic Zero- Sum code provides fewer average wire transitions per transaction (a metric for average power), with better or comparable coding efficiency. Several enhancements to the basic Zero-Sum ECU code are proposed: (i) the complete family of Zero-Sum codes is defined by exploring the feasible space of index weight assignments and permutations; (ii) a new code called Zero-Sumt which guarantees detection of up to 3-bit errors is presented; and (iii) a new class of codes called Zero-Sum*, which heuristically provides a high coverage of 2-bit correction, is presented. The second family of codes presented is called DI Bus-Invert . These codes are designed for the two-tiered cost function of reduced number of wire transitions and coding efficiency, while at the same time ensuring manageable hardware overheads. This work builds on an earlier synchronous bus-invert approach by Stan and Burleson, but with significant modifications to ensure that delay-insensitivity is guaranteed. To our knowledge, the DI Bus-Invert code is the first approach to migrate the core Stan and Burleson bus-invert techniques to delay-insensitive communication. When compared to the most coding-efficient systematic DI code (i.e. Berger) over a range of field sizes, the DI Bus-Invert codes had significantly fewer wire transitions per transaction, with comparable coding efficiency. The third code family combines the distinct strategies used in the Zero-Sum and DI Bus- Invert codes, to provide lower power for a DI error-correcting code. The most promising of these codes, called Selective Invert Bias, has significantly fewer average wire transitions than the Zero-Sum code, yet maintained the same error-correction capability. Supporting hardware for the Zero-Sum and DI Bus-Invert encoding schemes were implemented and evaluated. Results indicate that the hardware for Zero-Sum codes has only moderate area and delay overheads. In comparison, supporting hardware for the best non-systematic ECU codes has 3x to 10x greater area for larger field sizes. Similarly, the DI Bus-Invert code was shown to have significantly lower hardware overhead than that of the comparable non-systematic DI codes (i.e., m-of- n)." @default.
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• W2222414310 date "2011-01-01" @default.
• W2222414310 modified "2023-09-26" @default.
• W2222414310 title "Designing delay-insensitive codes for robust global asynchronous communication" @default.
• W2222414310 hasPublicationYear "2011" @default.
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